In July, Aspencore held a two-day virtual chiplet conference through its publications EE Times and embedded, Chiplets: Building a Future of SoCs. It was hosted by well-known industry journalists, Sally Ward-Foxton and Nitin Dahad. Let’s go over some of the highlights:
Lam Research
AI chip performance is enhanced by using advanced packaging. The Artificial Intelligence market is booming, with increasing applications, and by 2030 LAM expects the AI market to grow to $2T. (Figure 1)
Many of the industry’s current systems are powered by AI chips as shown in Figure 2:
Advanced packaging for AI should deliver the required performance, power, form factor, and cost.
Currently, the key packaging technology used for systems such as the Nvidia H100 is TSMC’s CoWoS using silicon interposers and HBM stacked memory (Figure 3). As IFTLE has discussed before, this is why there is such a current shortage of silicon interposer availability worldwide.
Zero ASIC
Andreas Olofsson, formerly DARPA program manager of the CHIPS program, offered this simplified chiplet definition:
“Chiplets are a tiny integrated circuit (IC), with partial functionality, designed to be combined with other chiplets within a package to create a complete chip.”
IFTLE likes it …simple and to the point. Again, chiplets ARE NOT simply tiny chips and the key terms in this completely correct definition are “partial functionality” and “must be combined with other chiplets within the package to form a complete chip” Chiplets must meet those two criteria.
During his presentation on their attempt to standardize chiplet architectures, Olofsson showed this list of chiplet success stories. (Figure 4)
He also made the interesting biological analogy that chiplets are “The amino acids of silicon systems” and that once chiplet functions are standardized, they can be recombined similar to how one created DNA strands, i.e. using the same building blocks in different combinations.
Blue Cheetah
Blue Cheetah discussed how the emerging chiplet ecosystems needed to enable innovative multi-vendor designs.
While much of today’s market is driven by the single-vendor model where all the chips and sometimes even the connection fabric is defined by one vendor, the industry knows it needs to move to a multi-vendor ecosystem and hopefully reach the holy grail of a plug-and-play chiplet solution.
Blue Cheetah claims HBM is the only existing example of a “plug-and-play” chiplet product. HBM chiplets are very tightly functionally, mechanically, and electrically specified by a standards body (JEDEC).
Requirements placed on the chiplet-to-chiplet interconnect vary widely with the application/product, i.e. package type, bandwidth, power, reach, footprint, protocols, … die-to-die (D2D) PHYs can be categorized by package type, bandwidth, reach, and hence energy-efficiency.
Blue Cheetah’s BlueLynx™ D2D interface platform reportedly allows one to rapidly configure and create highly optimized Universal Chiplet Interconnect Express (UCIe), Bunch of Wires (BoW) and custom D2D / link layer interconnect solutions.
Synopsys
Synopsys offered the following multi-die design methodology:
It also revealed that chiplet designs are expanding and are expected to become > 50% of multi-die designs by 2029.
Synopsys also went into a detailed discussion on how UCIe defines PHY variants for standard and advanced package technologies.
- UCIe-A with a dense floorplan takes advantage of high routing/bump density
- UCIe-S with coarse bump density and floorplan aligns with the density limitations of standard packages
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